Staff Design Verification Engineer, Tenstorrent
AI HW
$100-500k
Salary includes base and variable compensation targets
Building computers for AI
Open for applications
Building computers for AI
501-1000 employees
Open for applications
$100-500k
Salary includes base and variable compensation targets
501-1000 employees
Company mission
To bring unique solutions to the problems facing AI and machine learning.
Role
Who you are
- The successful candidate will have a strong background in verification techniques, excellent problem-solving skills, and a passion for delivering high-quality designs
- Senior verification expert with a proven record of validating complex, high-performance digital designs from concept to silicon
- Strong command of UVM, SystemVerilog, and advanced verification methodologies, with a deep understanding of RTL design and system-level behavior
- Comfortable operating as a technical lead—guiding verification strategy, mentoring engineers, and driving closure across large-scale programs
- Highly analytical and hands-on, with strong communication skills and a drive to deliver silicon that works exactly as designed
What the job involves
- We are seeking an experienced Staff Level Design Verification Engineer to join our dynamic and innovative team. As a Staff Design Verification Engineer, you will play a critical role in ensuring the quality and reliability of our digital designs through comprehensive verification methodologies
- Define and lead verification strategies for major IP and subsystem blocks across AI and compute architectures
- Architect and maintain reusable, scalable UVM environments and verification infrastructure to support multi-site development
- Drive coverage convergence, debug complex design and performance issues, and ensure quality signoff ahead of tape-out
- Collaborate with design, architecture, and validation teams to improve design-for-verification practices and streamline bring-up cycles
- What You’ll Learn
- How Tenstorrent verifies cutting-edge, massively parallel compute architectures for next-generation AI workloads
- Advanced techniques for functional and formal verification at scale, using modern simulation and emulation platforms
- System-level debug workflows that span hardware, firmware, and compiler layers
- How architectural choices made early in design flow through to power, performance, and functional validation outcomes
Application process
- Please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process
Our take
Advances in artificial intelligence apps, combined with a global chip shortage, are strong tailwinds for chip processor Tenstorrent. The semi-conducter developer is designing specialized chips for running artificial intelligence applications, building chips for what it calls "software 2.0".
The company’s unique approach is to build for this future software, which it believes will be written at a higher level. Combining this with conditional computing, Tenstorrent supports a scalable distributed network approach that is analogous to a human brain.
While the market for specialised AI hardware is destined to be gigantic, the company has to compete with a plethora of hopeful startups (as well as major tech companies like NVIDIA and Qualcomm). That said, Tenstorrent boasts an excellent trajectory so far, with its latest moves including unveiling its high-end Wormhole AI processors, and a partnership with LG which will see the development of chips for "Affectionate Intelligence".
Kirsty
Company Specialist at Welcome to the Jungle
Insights
52% employee growth in 12 months
Company
Funding (last 2 of 7 rounds)
Dec 2024
$700m
SERIES D
Jun 2024
$300m
LATE VC
Total funding: $1.3bn
Company HQ
Flemingdon Park, Toronto, ON
Leadership
Jim Keller
(CEO)Previously Senior VP of Silicon Engineering at Intel Corporation, VP of Autopilot Hardware Engineering at Tesla, Corporate VP and Chief Architect at AMD, and VP of Engineering at Apple.
Milos Trajkovic
(Co-Founder & Director of Hardware Engineering)Former Manager of Firmware Design Engineering at AMD, and FPGA design engineer at Signum Concepts.
Ivan Hamer
(Co-Founder)Former Consulting Software/Embedded Engineer at AMD, and Senior Software Developer at iNTERFACEWARE.
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