Mid Level ASIC Design Engineer, Tensordyne
Office located in Sunnyvale, CA
Next-generation AI inference systems
Posted today
Next-generation AI inference systems
101-200 employees
Posted today
Office located in Sunnyvale, CA
101-200 employees
Company mission
To build AI math, chips, hardware, and software from the zeroth layer up, rewriting the numbers so intelligence flows with a fraction of today's energy and cost.
Role
Who you are
- 3+ years of ASIC design experience with a demonstrable track record of RTL logic design in multi-million gate ASICs with Verilog or System Verilog
- Experience in IP integration, specifically CPU IP into SoC
- Knowledge of ARM/RISC-V/MIPS Architectures, Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation
- Familiarity with AMBA/APB/AXI Protocol
- Familiarity with processor peripheral interfaces like SPI, eMMC, *MII, GPIO, I2C ...
- Hands-on experience in all aspects of the ASIC development process with proficiency in front-end tools and methodologies
- Familiarity with low power design. UPF flow for defining power intent of chips with multiple power domains
- Previous experience with timing closure at high frequencies is a plus
- Interest to explore AI architectures for convolution, transformer and other kinds of workloads
- Self-starter and highly-motivated to work in a dynamic start-up environment
- B.S. (M.S. preferred) degree in Electrical or Computer engineering
What the job involves
- As a member of Tensordyne’s ASIC team, you will be responsible for the microarchitecture and design implementation of a high-performance and low-power convolutional neural network accelerator ASIC
- This ASIC’s design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to form an end-to-end vision perception module that achieves record-breaking computational performance at low power
- Your responsibilities will be wide-ranging and run the gamut of microarchitecture design and documentation, Verilog RTL implementation, selecting and integration 3rd-party IP blocks, working closely with design verification engineers, running frontend synthesis and working with a backend team on place-and-route guidance and timing closure
- Author/Understand micro-architecture specifications and participate in specification and test plan reviews
- Implement complex RTL designs
- Integrate CPU and other relevant IPs into the CPU sub-system
- Collaborate with the physical design team to resolve implementation and timing issues and to optimize power
- Analyze code coverage and provide feedback to the verification team to achieve coverage closure
- Perform diagnostic and post-silicon validation tests, as well as assist with software bring-up in the lab
Our take
The AI industry is growing fast, but it's also running into a big problem: power. LLMs need huge amounts of energy, adn the more compute you add, the higher the costs and technical challenges. Hyperscalers, cloud providers, and AI startups all face the same question, how to scale AI efficiently without wasting power. And the search for smarter, more efficient solutions is becoming critical.
Tensordyne, formerly Recogni, began as a maker of automotive edge chips but quickly pivoted to focus on data center AI. The team realized that the future of AI would be defined by large-scale inference, where efficiency and scalability matter most. Their approach goes beyond hardware tweaks, using a logarithmic math system that slashes energy use while improving accuracy, making AI faster, cheaper, and more sustainable.
LLMs and data center AI are consuming massive amounts of power, and this is becoming a real concern. Tensordyne's efficient hardware and innovative logarithmic math can cut energy use drastically while keeping performance high, helping ensure AI can grow sustainably without overloading costs or the environment.
Freddie
Company Specialist at Welcome to the Jungle
Insights
6% employee growth in 12 months
Company
Funding (last 2 of 3 rounds)
Feb 2024
$102m
SERIES C
Feb 2021
$48.9m
SERIES B
Total funding: $175.9m
Company HQ
Sunnyvale, CA
Leadership
RK Anand
(Co-Founder & CPO)RK comes from a Computer Engineering background and has gained extensive experience in managing and founding multiple technology enterprises.
Marc Bolitho
(CEO)Marc previously spent over 6 years at ZF Group in various roles, including Senior VP and GM of ADAS Business Unit. Prior to that, he spent nearly 22 years at TRW Automotive in roles including Chief Engineer and GM and Engineering DIrector of Global Passive Safety Electronics.
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