CPU Core Design Verification Testbench Lead, Tenstorrent
Next-generation computing company building computers for AI
Be an early applicant
Next-generation computing company building computers for AI
1001+ employees
Be an early applicant
1001+ employees
Company mission
To bring unique solutions to the problems facing AI and machine learning.
Role
Who you are
- You bring 8+ years in CPU verification, CPU testbench development, or closely related digital design
- You have deep hands-on experience building and owning CPU core-level testbenches, not just using existing environments
- You know high-performance out-of-order CPU microarchitecture in depth
- You are comfortable developing testbench infrastructure in CVM methodology, with UVM experience as a strong plus
- You work comfortably across RTL, waveforms, logs, regressions, and cross-functional debug with design, DV, emulation, and post-silicon teams
- You are comfortable using AI-assisted verification workflows to improve debug, stimulus creation, and coverage analysis, while applying strong engineering judgment to validate results
- We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting
What the job involves
- You will own CPU core-level testbench development and verification, shaping how our out-of-order RISC-V CPUs behave in silicon
- Lead hands-on CPU core-level testbench development for high-performance out-of-order RISC-V cores
- Own and evolve CVM-based verification methodology, infrastructure, and reusable testbench components
- Plan and drive functional verification for CPU core features, ISA behavior, and microarchitectural scenarios
- Develop UVM, assembly, C/C++ stimulus, and C++ functional models for RISC-V extensions and un-core components such as APIC and IOMMU
- Debug regressions, close coverage, and improve core, cluster, and chip-level testbenches across simulation, emulation, and post-silicon environments
- Develop testbench and tooling infrastructure that combines Python orchestration with specialized AI agents to accelerate triage and root-cause analysis across logs, waveforms, and verification databases
- What You Will Learn
- How Tenstorrent designs and validates high-performance RISC-V CPU cores and clusters
- Techniques for building scalable CPU testbench infrastructure across core, cluster, and chip-level environments
- Ways to apply CVM methodology to complex CPU verification and debug workflows
- Techniques for spanning pre-silicon, emulation, and post-silicon verification with shared stimulus
- How to scale coverage, debug, and infrastructure across multiple CPU programs within Tenstorrent’s broader compute roadmap
- How Tenstorrent applies AI across the DV lifecycle — from test planning and stimulus through regression debug, triage, and coverage analysis — using workflows designed to keep context tight and outputs auditable
Our take
Tenstorrent is a US- and Canada-based semiconductor startup specializing in processors for AI workloads. Rather than building gneral-purpose CPUs or GPus, the company develops custom chips and sofrware optimized for running moder AI models. As demand for AI accelerates, and as a global chip shortage reshapes the semiconductor industry, these trends have become strong tailwinds for Tenstorrent.
The company’s unique approach is to build for this future software, which it believes will be written at a higher level. Combining this with conditional computing, Tenstorrent supports a scalable distributed network approach that is analogous to a human brain.
While the market for specialized AI hardware is destined to be gigantic, the company has to compete with a plethora of hopeful startups (as well as major tech companies like NVIDIA and Qualcomm). That said, Tenstorrent boasts an excellent trajectory so far, with its latest moves including unveiling its high-end Wormhole AI processors, and a partnership with LG which will see the development of chips for "Affectionate Intelligence".
Kirsty
Company Specialist at Welcome to the Jungle
Insights
52% employee growth in 12 months
Company
Funding (last 2 of 7 rounds)
Dec 2024
$693m
SERIES D
Jun 2024
$300m
LATE VC
Total funding: $1.3bn
Company HQ
Flemingdon Park, Toronto, ON
Leadership
Jim Keller
(CEO)Previously Senior VP of Silicon Engineering at Intel Corporation, VP of Autopilot Hardware Engineering at Tesla, Corporate VP and Chief Architect at AMD, and VP of Engineering at Apple.
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