Staff Digital Verification Engineer, Eliyan
Digital
Performance improvement for chiplet-based systems
Open for applications
Performance improvement for chiplet-based systems
21-100 employees
Open for applications
21-100 employees
Company mission
To enable the scalable, power-efficient computing architectures required for the next wave of AI and advanced computing workloads.
Role
Who you are
- Masters or Ph.D in Electrical Engineering and related fields with 6+ years of experience
- Hands on experience in verification of serial transmission protocols and products (preferably in retimer, gearbox, Ethernet PMA/PCS logic)
- Strong expertise in UVM, test environment and assertion coding with SystemVerilog
- Proficiency in 3 rd party tools for regression management and coverage analysis
- 3+ experience working on Ethernet 802.3 standards’ clauses related to 100G, 200G, 400G, 800G; Auto-Negotiation and Link Training
- Knowledge of DRAM Controllers/PHYs and HBM Memory a plus
- Strong bias for innovations across all aspects of digital verification including automation of mundane activities and methods for quality improvement
- Experience in verifying 3 rd party mixed signal IPs as well as integration of VIPs
- Proven track record of being part of a start-up like environment
What the job involves
- As an Eliyan staff digital verification engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility
- You will be developing state-of-the-art testbenches and unit/chip level test cases for best-in-class PHYs and Controllers
- You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits
- Develop and execute verification plans for connectivity IPs and Chiplets
- Create and maintain SystemVerilog/UVM-based verification environments
- Write and debug SystemVerilog/UVM compliant test cases for block and chip level
- Maintain a regression environment for enabling design CI/CD pipelines
- Collaborate with design engineers to ensure design quality with continuous microarchitecture, test-plan, and coverage reviews
- Develop, maintain, and track various test plan items and progress towards RTL freeze
- Stay up to date with industry trends, emerging technologies and progress in standards’ bodies
- Ensure IP compliance with Ethernet standards (IEEE 802.3)
- Integration 3rd party VIPs and coordinate feature/bug tracking requests
- Perform in the capacity of a technical leader for junior verification engineers
- Create, improve, maintain DPI based FW simulation environments
- Create, improve, maintain GLS environments for functional and power simulations
Our take
In order for technology like artificial intelligence to work at its peak, the hardware we use needs to support high performance. Eliyan is working to make peak-performance hardware a reality by eliminating the so-called "memory wall" that hinders high-performance applications.
Essentially, this problem exists because the current memory infrastructure works slower than the high-performance applications themselves. Eliyan combats this by supplying chiplet interconnect technology, which enables the tiny building blocks of computing structure to be linked together on the same device.
It's a complex undertaking, but a valuable one - and the idea has seen Eliyan raise considerable backing from major AI and compute players. This not only showcases a vote of confidence from the sector, but also enables the company to move forward with the commercialization of its offerings.
Freddie
Company Specialist at Welcome to the Jungle
Company
Funding (last 2 of 3 rounds)
Jan 2026
$50m
LATE VC
Mar 2024
$60m
SERIES B
Total funding: $150m
Company HQ
Santa Clara, CA
Leadership
Ramin Farjadrad
(Co-Founder & CEO)Former CTO and VP of Networking/Automotive PHYs at Marvell Semiconductor. Was Chair of the Technical Committee at NAV Alliance, Co-Founder and CTO at Aquantia and Senior Principal at Rambus.
Syrus Ziai
(Co-Founder & COO)Previously VP of Engineering at NUVIA and Qualcomm, SVP of Engineering at PsiQuantum and VP of Worldwide Engineering at Ikanos Communications. Has also held CEO positions in the past.
Patrick Soheili
(Co-Founder)Managing Director at Ridgeview Venture Partners. Was a VP at eSilicon, as well as President and CEO at ON DEMAND Microelectronics and at Cradle Technologies.
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