Senior Principal Program Manager, Astera Labs

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field
• 10+ years of experience in ASIC/SoC development or silicon program execution, including 3+ years in technical program management, engineering program management, or technical leadership
• Experience managing pre-silicon ASIC development flows, including architecture planning, RTL design, functional verification, synthesis, DFT, physical design, timing closure, signoff, and tapeout
• Experience with advanced process nodes and high-performance ASIC/SoC development
• Strong understanding of ASIC development milestones from product requirements through final GDS handoff
• Familiarity with EDA flows, CAD infrastructure, IP integration, PDK readiness, foundry requirements, and vendor dependency management
• Experience with pre-silicon validation platforms such as simulation, emulation, FPGA prototyping, or hardware/software co-validation
• Experience driving complex cross-functional programs with multiple engineering teams, technical dependencies, external vendors, and aggressive schedules

Desirable

• As a Sr. Principal Program Manager, ASIC Design at Astera Labs, you will own the cross-functional execution framework for advanced ASIC programs from early planning through tapeout. You will drive milestones, dependencies, execution reviews, decision-making forums, risk management, and tapeout readiness across multiple engineering teams
• You will partner closely with architecture, RTL design, functional verification, emulation, DFT, synthesis, physical design, CAD, IP, product management, engineering leadership, and external partners
• This is a high-impact role for a technical program leader who can operate in a fast-moving environment, manage ambiguity, drive accountability, and establish scalable execution practices across complex silicon development programs
• Lead pre-silicon execution of complex ASIC and subsystem programs from concept through tapeout
• Own program plans, schedules, milestones, dependencies, risk registers, dashboards, and executive-level status reporting
• Drive pre-silicon and NPD phase-gate execution from kickoff through final GDS handoff, ensuring cross-functional readiness across architecture, RTL, verification, DFT, physical design, signoff, and tapeout
• Drive cross-functional alignment across architecture, RTL design, verification, emulation, DFT, synthesis, physical design, CAD, IP integration, product management, and external partners
• Track IP delivery, PDK updates, CAD/EDA flow readiness, tool dependencies, and foundry requirements
• Partner with Post-Silicon PM and Validation teams to absorb feedback from post silicon bring up, including bug reports and Si issues
• Identify execution risks, lead risk mitigation plans, and drive trade-off decisions across scope, schedule, resources, and quality
• Communicate program health, risks, dependencies, and decisions clearly to engineering teams, senior leaders, executives, and external partners
• Establish scalable program management practices, operating rhythms, decision forums, documentation standards, and communication mechanisms, lead constant improvement