Senior ASIC Design Engineer, Tarana Wireless

• BSEE required/MSEE preferred
• 5-12 years of experience in SoC design
• Experience with Synthesis, Lint, CDC and other standard ASIC development tools
• Proficient in Verilog and C
• Working knowledge of scripting languages such as Python
• Excellent communication skills

Desirable

• The Senior ASIC Engineer will work on complex ASIC designs for our point to multipoint wireless products
• Architecture and micro-architecture of digital subsystems
• RTL design of digital circuits using Verilog
• Frontend design development and integration of large ASIC designs including: Integration of Processors, Bus, Memory, and Interface IPs
• Chip level integration and verification
• RTL design and integration of large functional blocks in the modem - Development, assessment and refinement of RTL design to target power, performance, area and timing goals
• Write design documents including detailed interface descriptions and design descriptions
• Work with Verification Engineers to develop specifications and test plans. Ensure robust design and complete coverage
• Work with Emulation teams to test the design on various emulation platforms
• Work with Software and Systems teams on system verification and system integration
• Writing test cases and test benches to verify functionality of designs