Senior Design Verification Engineer, Astera Labs

• We are looking for Senior Design Verification Engineers with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs
• Experience with System Verilog, C, C++, Python or other scripting languages would be a plus
• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Masters is preferred
• ≥5 years’ experience verifying and validating complex SoC for Server, Storage, and Networking applications
• Knowledge of industry-standard simulators, revision control systems, and regression systems
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in the US and start immediately
• Experience with full verification lifecycle based on System Verilog/UVM/C/C++
• Proven ability to mix and deploy hybrid techniques as in both directed and constrained random
• Experience with different ways to bug and coverage hunting. Experience in formal methods is a plus
• Must be able to work independently to develop test-plans, and related test-sequences to generate stimuli and work collaboratively with RTL designers to debug failures

Desirable

• Using your coding and problem-solving skills, you will contribute to the functional verification of the designs
• You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage
• You’ll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms
• Identify and write all types of coverage measures for stimulus and corner-cases. Close coverage to identify verification holes for high quality tape-out