ML Compiler Software Engineering Technical Lead, d-Matrix
$196-300k
+ Equity + Bonus
3 days a week in office (Santa Clara, CA)
AI computing and efficiency software
Open for applications
AI computing and efficiency software
201-500 employees
Open for applications
$196-300k
+ Equity + Bonus
3 days a week in office (Santa Clara, CA)
201-500 employees
Company mission
To unleash the potential of generative AI to power the transformation of technology.
Role
Who you are
- As such, we are seeking an AI compiler expert with experience in the TVM, Glow or preferably, the MLIR project
- Also important is familiarity with the LLVM project
- Experience mapping graph operations to many-core processors (or spatial fabrics) would be desirable
- BS / MS Preferred in Computer Science or equivalent with 12+ years in ML Compiler
- Experience establishing, growing and/or developing engineering teams (and software teams in particular)
- Experience with leading agile development methods is preferable including coordinating scrums, managing sprints and project task tracking with Kanban boards or similar
- Experience running code reviews, bug tracking meetings, familiarity and experience with CI/CD flows
- Managing interdependencies with other teams in order to meet milestones and target levels of performance
- Excellent documentation and presentation skills
What the job involves
- The Compiler Technical Lead role is driving the design and implementation of the MLIR-based compiler framework
- In this role, you will be overseeing the development of the compiler that partitions and maps large-scale NLP models to our scalable, multi-chiplet, parallel processing architecture with hundreds of digital in-memory tensor processors, vector processors, data shaping processors and both on-chip and off-chip memory
- The compiler will also coordinate the scheduling of parallel tasks onto the processors, data movements and inter processor synchronization
- The many-pass compiler architecture requires graph optimization passes, constant folding, data reshaping, padding, tiling and various other backend-specific operations
- The software will support a split offline/online mapping process with just-in-time mapping to chiplets, processors and DDR memory channels
- This role requires collaborating with the HW and SW architecture team, the Pytorch front-end pre-processing team, the data science numerics team, AI kernel team, SW test group, the benchmark group and the teams developing the various simulator and emulation platforms
- It is central to the overall efficiency of the solution
- This role includes technical leadership aspects: specifically the motivation, engagement, goal setting, performance tracking, objective setting and performance management
- This role does NOT require hardware design or verification experience
- That said, an understanding of the trade-offs made by processor architects when implementing accelerators for DNNs, DCNNs, transformer models and attention mechanisms is useful - especially when it comes to mapping very large NLP models to such architectures
Our take
d-Matrix is redesigning how AI gets done, tackling the limit f traditional chips with its Corsair platform. Using digital in-memory computing and a chiplet-based design, it delivers fast, power-efficient AI interface that's built for today's data-heavy models, without the energy overload.
Recently, the company has been making some serious moves. Its secured substantial funding, with backing from Microsoft, and partnering with HTEC to boost its software capabilities. With Corsair already showing serious speed gains over GPUs like Nvidia's H100, d-Matrix is proving it can deliver real-world performance at scale.
But instead of competing head-on with GPU giants, d-Matrix is focusing on where AI meets people. And with AI growing fast, especially for interactive and generative applications, d-Matrix is building the hardware that helps AI keep up with this demand.
Freddie
Company Specialist at Welcome to the Jungle
Company
Funding (2 rounds)
Sep 2023
$110m
SERIES B
Apr 2022
$44m
SERIES A
Total funding: $154m
Company benefits
- Equity
- Health care
- Flexible time-off
- Paid paternity leave
- 401k retirement plan
- Remote & hybrid working model
- Work with world-leading engineers and researchers
- Peer coaching & development
- Team-building activities
- Happy hours
- Free food and snacks
- On-site fitness center
Company HQ
Santa Clara, CA
Leadership
Sid Sheth
(Co-Founder, CEO & President)Previously Director at NetLogic Microsystems, Director of Marketing at Broadcom Inc and SVP/GM at Inphi Corporation.
Sudeep Bhoja
(Co-Founder & CTO)Previously CTO at Inphi Corporation, Technical Director at Broadcom and Chief Architect at Big Bear Networks.
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