Senior Staff Design Verification Engineer, Lightmatter

• If you're passionate about tackling complex challenges, making an impact, and being an expert in your craft, join our team of brilliant scientists, engineers, and accomplished industry leaders
• Bachelor’s degree in Electrical Engineering, Computer Engineering, a related field, or equivalent experience
• 12 years of design verification and SystemVerilog experience
• 2+ years of experience in python
• Expertise in developing the UVM library
• Experience with simulators such as Xcelium, ModelSim, Questa, or VCS

Desirable

• As a Design Verification Engineer at Lightmatter, you will find yourself at the heart of a dynamic, interdisciplinary team
• Your role will involve close collaboration with our digital design experts, using UVM testbench techniques to rigorously verify their designs
• Your responsibilities will include working alongside photonic and analog designers, gaining a deep understanding of their innovative designs, and applying Real Number Modeling (RNM) and AMS verification methods
• This critical function ensures the integrity of their work
• We are hiring Design Verification Engineers at multiple levels
• Your interaction with the Architecture team will be crucial in comprehending system requirements and spearheading performance verification
• This role offers a unique platform to enhance your skills across a spectrum of areas including UVM, AMS modeling, mixed-signal verification, formal verification, emulation, and both performance modeling and verification
• Engage collaboratively with teams specializing in digital, photonics, and analog design to develop comprehensive test plans
• Design and implement UVM testbenches for both subsystem-level and full-chip verification
• This includes debugging testbenches, resolving issues, achieving high coverage, and overseeing the final sign-off on Design Verification (DV)
• Develop Real Number Models (RNM) for photonics and analog circuits, conduct AMS verification in conjunction with UVM, and ensure precise model representation
• Contribute significantly to the development of the Golden Reference Model (GRM) for design verification
• Play an integral role in the execution of emulation and formal verification for DV purposes