Hardware Engineering Intern, d-Matrix
PCB Layout Automation & AI Tooling
$30 – $59 per hour
3 days a week in office (Santa Clara, CA)
AI computing and efficiency software
Be an early applicant
AI computing and efficiency software
201-500 employees
Be an early applicant
$30 – $59 per hour
3 days a week in office (Santa Clara, CA)
201-500 employees
Company mission
To unleash the potential of generative AI to power the transformation of technology.
Role
Who you are
- Current Student: Pursuing a BS, MS, or PhD in Electrical Engineering, Computer Engineering, or Computer Science
- PCB Fundamentals: Basic understanding of PCB design flow (Schematic -> Layout -> Fabrication) and familiarity with at least one EDA tool (Allegro, Altium, or KiCad)
- Programming Skills: Strong proficiency in Python. Experience with APIs, data parsing (JSON/XML), or automated tool-chaining is highly preferred
- First-Principles Thinking: A passion for challenging the status quo of "how things have always been done" in hardware design
Desirable
- Familiarity with AI/ML concepts, particularly Reinforcement Learning or Generative Models applied to physical design
- Experience with GitHub and version control for hardware projects
- Exposure to high-speed design concepts (PCIe, DDR, SerDes)
What the job involves
- 12 Week Program: June 1st - August 21st or June 22nd - September 11th
- At d-Matrix, we are building the future of AI compute
- To do that faster, we need to rethink how hardware is designed
- We are looking for a forward-thinking Hardware Engineering Intern to join our team and focus on the cutting edge of EDA (Electronic Design Automation) and AI-driven layout
- Your mission will be to evaluate, integrate, and automate PCB layout workflows using emerging AI-agent technologies and generative AI design tools
- You will bridge the gap between traditional hardware design and the future of automated, agentic workflows
- AI Tool Evaluation: Lead the internal evaluation of AI-driven layout platforms
- Benchmarking their ability to handle high-speed constraints, complex stack-ups, and power delivery requirements against traditional manual routing
- Workflow Automation: Develop scripts (Python, SKILL, or TCL) to bridge the gap between d-Matrix’s standard EDA tools (Cadence Allegro/OrCAD) and AI layout agents
- PCB Design Support: Assist Senior Layout Engineers in preparing design data (schematics, netlists, and constraint files) for automated routing engines
- Constraint Translation: Work on "translating" complex hardware constraints (differential pairs, length matching, and Z_{target} for PDN) into formats that AI agents can ingest and execute accurately
- Performance Analysis: Conduct post-layout analysis on AI-generated designs, comparing Signal Integrity (SI) and Power Integrity (PI) metrics against human-designed baselines
Our take
d-Matrix is redesigning how AI gets done, tackling the limit f traditional chips with its Corsair platform. Using digital in-memory computing and a chiplet-based design, it delivers fast, power-efficient AI interface that's built for today's data-heavy models, without the energy overload.
Recently, the company has been making some serious moves. Its secured substantial funding, with backing from Microsoft, and partnering with HTEC to boost its software capabilities. With Corsair already showing serious speed gains over GPUs like Nvidia's H100, d-Matrix is proving it can deliver real-world performance at scale.
But instead of competing head-on with GPU giants, d-Matrix is focusing on where AI meets people. And with AI growing fast, especially for interactive and generative applications, d-Matrix is building the hardware that helps AI keep up with this demand.
Freddie
Company Specialist at Welcome to the Jungle
Company
Funding (last 2 of 3 rounds)
Nov 2025
$275m
SERIES C
Sep 2023
$110m
SERIES B
Total funding: $429m
Company benefits
- Equity
- Health care
- Flexible time-off
- Paid paternity leave
- 401k retirement plan
- Remote & hybrid working model
- Work with world-leading engineers and researchers
- Peer coaching & development
- Team-building activities
- Happy hours
- Free food and snacks
- On-site fitness center
Company HQ
Santa Clara, CA
Leadership
Sid Sheth
(Co-Founder, CEO & President)Previously Director at NetLogic Microsystems, Director of Marketing at Broadcom Inc and SVP/GM at Inphi Corporation.
Sudeep Bhoja
(Co-Founder & CTO)Previously CTO at Inphi Corporation, Technical Director at Broadcom and Chief Architect at Big Bear Networks.
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