Silicon Architect, Normal Computing
Diffusion ASICs
$234-298.3k
+ Equity
Generative AI for enterprise
Be an early applicant
Generative AI for enterprise
21-100 employees
Be an early applicant
$234-298.3k
+ Equity
21-100 employees
Company mission
To bridge artificial intelligence to the most sensitive industrial and advanced manufacturing applications around the globe.
Role
Who you are
- A degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent work experience. PhD welcome but not required; the bar is the work, not the credential
- Substantial experience in architecture or microarchitecture of high-performance digital systems. AI accelerators, compute engines, or similarly complex logic. You have shaped the structures inside a chip, not just consumed them from the outside
- Fluency moving between algorithm-level analysis and hardware specification. You can read a profile of a workload and translate it into datapath widths, pipeline stages, and area/power estimates without losing the thread on either side
- Experience with simulation-driven architecture. You have used cycle-accurate or analytical models to make and defend design decisions before RTL exists, and you know which questions each tool can answer and which it cannot
- Familiarity with quantization and reduced-precision approaches for inference and their implementation implications. You understand the cost of a bit at the hardware level, not just the model level
- Experience writing microarchitecture specifications and working closely with RTL engineers through implementation. Your specs are read, not just filed
- Proficiency in Python or C++ for performance modeling and analysis, and familiarity with SystemVerilog or equivalent RTL
- Comfort operating in an environment where the architecture is actively being discovered alongside the work. You do not need the answer to be already known to make progress on it
- This role is not for everyone. You will spend years on a chip that does not exist yet, defending decisions that cannot be fully validated until silicon comes back, on a bet most of the industry has not made
- The people who thrive here, run toward the hard stuff
- They are steady in ambiguity, comfortable when the data is incomplete, and they take the hardest problem on the board first because that is where the answer is hiding
- They are not waiting for the architecture to be handed to them. They want to be the ones who define it
- If you have spent your career suspecting you are one of those people, this is where you find out. The chip you help build will be the silicon behind a generation of image and video AI — the work people watch, the work people create with, the work that shapes what the next decade of visual computing looks like
What the job involves
- Look at the AI accelerator roadmaps coming out of every major silicon company right now and you will notice something strange: they are all building the same chip
- Bigger systolic arrays. More HBM. More of the same architecture, scaled harder. The industry has placed a collective bet that the way to win the next decade of AI inference is to refine the GPU paradigm until it cannot be refined any further
- We know that bet is wrong
- Normal is building ASICs purpose-built for image and video diffusion inference, grounded in the physics of computation rather than the assumptions everyone else has inherited
- The compute substrate has to be invented, not specified, and we are looking for the person who wants to help invent it
- You will work directly alongside our lead architect and research engineers, contributing across the full architecture stack: compute core microarchitecture, memory subsystem, interconnect, and the FPGA prototyping that proves the decisions before silicon. The team is small. The scope is wide
- The architecture is being shaped now, not refined, and your contributions will be visible in the chip when it tapes out
- If the appeal of working on a chip that has to be invented is greater to you than iterating on one that already exists, keep reading
- Help define the architecture and microarchitecture of novel AI accelerator compute blocks. PE array design, datapath organization, and support for efficiency techniques such as sparsity exploitation and reduced-precision computation. The compute tile is the surface where Normal's research advantages have to show up in silicon, and you are one of the people responsible for making sure they do
- Translate workload analysis and research findings into hardware specifications. Identify where architectural innovation creates the most leverage, define the structures that realize it, and produce microarchitecture documents unambiguous enough for RTL engineers to implement against. You work closely with them through implementation, not over the wall from it
- Reason across the full stack and defend PPA tradeoffs at every level. Move between algorithm-level workload behavior, memory hierarchy, on-chip interconnect, and physical design constraints. Make the call when the data is incomplete, and articulate why under scrutiny from the lead architect and the research team
- Partner with the compiler lead on ISA co-design. The compute tile must be compilable and programmable, not just simulatable. The programming model and the microarchitecture are defined together, and you are accountable for both sides meeting in the middle
- Own the FPGA prototyping work. Scope what the FPGA implementation actually proves, drive the implementation through to bring-up, and use it to de-risk architecture decisions before tapeout. You decide which questions are worth answering in FPGA versus cycle-accurate simulation
- Stay current with the AI accelerator research landscape and be able to articulate clearly where Normal's approach differs from existing solutions and why that matters. This is a research-adjacent seat and you are expected to read, not just consume
Our take
As the rate of AI adoption accelerates, Normal Computing is positioning itself to make advanced AI more usable and scalable for enterprises, where ris,, reliability and energy constraints remain major barriers. While generative AI has so far flourished in consumer settings, enterprise use has lagged due to concerns around control, auditability and cost. Normal's approach hopes to unlock these more complex use cases by rethinking how AI systems are built and deployed from the ground up.
At the core of the company's strategy is its Probabilistic AI framework, which gives customers greater control over reliability, adaptivity and auditability when working with private data. This software vision is now being reinforced by a major hardware milestone: the successful tape-out of CN101, the world's first thermodynamic computing chip. By harnessing natural physical dynamics such as stochasticity and noise, CN101 is designed to dramatically improve energy efficiency on AI and scientific workloads, allowing tasks like complex underwriting, probabilistic sampling and large-scale optimization to run faster and within fixed data centre energy budgets.
By tackling both the trust and energy bottlenecks that limit enterprise AI adoption, Normal is expanding its ambition from AI software into next-generation compute infrastructure. With a clear roadmap from CN101 to more advanced chips over the next few years, and substantial funding behind its R&D efforts, the company has the potential to play a meaningful role in shaping how high-performance AI scales in practice.
Freddie
Company Specialist at Welcome to the Jungle
Company
Funding (last 2 of 4 rounds)
Mar 2026
$50m
EARLY VC
Nov 2024
$67m
GRANT
Total funding: $134m
Company HQ
Civic Center, New York, NY
Leadership
Faris Sbahi
(Co-Founder & CEO)Previously worked as a Research Scientist at X, the moonshot factory, a Software Engineer at Google, and as a Forward Deployed Engineer at Palantir Technologies.
Matthias Tan
(Co-Founder & COO)Venture Partner at NextGen Venture Partners. Former Principal of Strategy and Partnerships at X, the moonshot factory, and Director of Product and Partnerships at Pony.ai.
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