Verification Engineer, Riverlane

• Demonstrable commercial experience in functional verification, including ownership of verification planning and strategy
• A proactive and collaborative person who actively shares feedback and can independently define the scope of work
• Proven experience of testbench design with verification frameworks like UVM/OVM
• Knowledge of SystemVerilog assertion (SVA)
• Exposure to different programming languages, such as C, C++ and Python

Desirable

• You will work with our talented team of hardware designers and embedded software engineers to produce a fully verified, trusted and performant solution. With full visibility of the entire stack, you will own everything verification related
• Proactively work with designers and architects to define verification plans based on design specifications. You will own, define and track detailed test plans for different blocks and system level
• Implement scalable testbenches, including checkers, reference models and coverage groups in SystemVerilog. You will implement self-testing, directed and random tests
• Maintain the design verification environment, keeping track of regression, coverage metrics and bugs