Senior ASIC Physical Design Engineer, HP Enterprise
$153.5-310.5k
Office located in San Jose, CA
Global edge-to-cloud company
Posted today
Global edge-to-cloud company
1001+ employees
Posted today
$153.5-310.5k
Office located in San Jose, CA
1001+ employees
Company mission
To help customers use technology to turn ideas into value, and empower them to transform industries, markets and lives.
Role
Who you are
- BS degree in electrical engineering, computer engineering, or a related field with 3+ years of experience in block or full-chip physical design, or
- MS degree in the above fields with 2+ years of related experience
- Deep design experience in large SoC designs, including IP integration
- Extensive knowledge and practices in Physical Design, including physically aware synthesis, floor-planning, place & route, CTS, and repeater/feedthrough
- Experience in implementing power-grid and clock network at block level
- Knowledge of basic SoC architecture and HDL languages like Verilog to work with the logic design team for timing fixes
- Experience in physical design verification to debug LVS/DRC/ERC/ANT issues at chip/block level
- Experience in custom place and route
- Exposure to 2.5D/3D packaging is preferred
- High performance and large chip design experience is preferred
- Exposure to DFT is preferred
- Proficiency in writing Linux shell scripts in Perl, TCL, and Python
- Real chip tapeout experience in 7nm and/or below with a successful signoff track record
- Self-motivated with strong problem-solving and debugging skills
- Ability to work effectively in a dynamic group environment
What the job involves
- As a block-level Physical Design Engineer, you will contribute to all phases of physical design from RTL to the delivery of our final GDSII. Your responsibilities include:
- Implement physical design at the large SoC block level from RTL to GDSII, creating a design database ready for manufacturing
- Interact with IP vendors to understand IP integration requirements and integrate all blocks, IPs, and sub-chips at a large SoC level
- Collaborate with the packaging team on Microbump/Probe Bump/Bump/Pad placement
- Build block level floorplan, including block pins, macro placement and alignment, power grid, etc
- Develop the block-level clock network and clock structure in collaboration with clock experts
- Generating block/chip-level static timing constraints
- Arrange, analyze, and optimize feedthrough and repeaters among all blocks
- Perform block-level place and route, including custom place & route, ensuring the design meets timing, area, power constraints, and all sign-off criteria
- Generate and implement ECOs to fix timing, signal integrity, EM/IR violations, PV, and complete formal verification
- Integrate DFT into physical design, ensuring alignment with overall test strategies and manufacturing requirements
- Run Physical Design verification flow at chip/block level, fixing LVS/DRC/ERC/ANT violations
- Collaborate closely with architecture, frontend design, DV, and package teams to ensure cohesive design implementation and successful project tapeouts
Our take
Hewlett Packard Enterprise is a global edge-to-cloud company that delivers unique technology solutions. The company enables its clients to unlock value from all of their data, providing actionable insights that accelerate business outcomes.
Founded in 1937, the company has grown to become one of the world’s leading enterprise technology companies. Among its offerings are cloud services, high-performance computing & AI, Intelligent Edge, and storage – to help with business model development, engagement, performance, and more.
HP Enterprise has been incredibly focused on the optimization of its current offerings as well as setting the standard of future innovation with its ever-expanding portfolio. For example, its HPE Machine Learning Development System (launched in April 2022) removes barriers traditionally seen when incorporating AI and ML into products and services, enabling companies to realize the full potential of AI.
With its range of product announcements and launches (including HPE ProLiant Gen11 and HPE GreekLake) coupled with its strategic partnerships and acquisitions, HP Enterprise is well set to lead the next generation of enterprise software solutions.
Steph
Company Specialist at Welcome to the Jungle
Insights
11% employee growth in 12 months
Company
Company benefits
- Competitive base pay and benefits
- The chance to earn an annual bonus based on performance
- Recognition for your contributions, and potential participation in long-term incentives like annual equity awards
- Subsidized health insurance, retirement programs and paid time off, including an industry-leading maternity and paternity leave package
- A hybrid, flexible work model that ensures connectivity, a commitment to our culture and continued impact for team members
- Opportunities for personal and professional development to help you reach your career goals
Leadership
Antonio Neri
(President & CEO)Previously served as the company's Executive VP before becoming the President & CEO. Worked at HP in a number of roles, including Senior VP and General Manager.
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