Senior ASIC Digital Design Manager , Avicena Tech

Salary not provided

Expert level

San Francisco Bay Area

Office located in Sunnyvale, CA

High bandwidth semiconductor interconnects

Open for applications

High bandwidth semiconductor interconnects

1-20 employees

B2BManufacturingTelecommunicationsCloud Computing

Open for applications

Salary not provided

Expert level

San Francisco Bay Area

Office located in Sunnyvale, CA

1-20 employees

B2BManufacturingTelecommunicationsCloud Computing

Company mission

To design high density interconnects that break the current paradigm and enable new architectures.

Job

Company

Role

Who you are

MS or PhD in Electrical Engineering
10 years of experience in digital design from specs to architecture, design, bench testing and all the way to high volume production
Deep understanding of RTL design for high speed datapath and signal processing, experience with different bus architectures, MCU integration
Knowledge of the backend flow and ability to check STA reports and resolve any issues that require RTL change
Ability to supervise the verification effort
3+ years of Management experience

What the job involves

Develop micro architecture for the digital section of the ASIC
Write RTL in verilog for the blocks and simulate them
Supervise the verification team and ensure they have sufficient coverage
Develop SDC files for the backend
Interact with the backend engineers to make sure the design meets all requirements such as STA, IR, etc

Our take

Copper has been the industry standard for chip-to-chip interconnects since it was introduced by IBM back in 1997. Now, however, the computational demands of more complex systems like AI, machine learning, and cloud systems are too high: copper interconnects are creating bottlenecks thanks to sub-optimal latency and power consumption. Avicena Technology has developed a new system - it could be a game changer.

The company’s ‘LightBundle’ solution uses micro-LEDs to create ultra-dense, low-latency, low-cost, and low-power optical interconnects, thereby facilitating the kind of high-performance architecture that’s in increasingly high demand as digital infrastructure becomes more complex.

It’s a solution that’s attracted healthy funding from major players including Samsung Catalyst Fund and Cerberus Capital Management. This suggests substantial faith in Avicena Technology’s ambition that its technology could help unlock the future of distributed high-performance computing and disaggregated architecture. Although a relatively modest outfit for now, Avicena Technology’s advances could prove highly influential over the coming years.

Kirsty

Company Specialist at Welcome to the Jungle

Insights

Glassdoor (5)

Company

Funding (2 rounds)

Aug 2022

$25m

SERIES A

Nov 2019

$6.5m

EARLY VC

Total funding: $31.5m

Company benefits

Medical, Dental , Vision & Disability —
90% contribution from Avicena for you and your family
401K
Stock options
Free food!

Company values

Team collaboration
Being self-driven and self-directed
Intellectual and career growth
Creative problem solving
Informal and fun work environment

Company HQ

Mountain View, CA

Articles

Avicena lands $25 million in Series A funding

Copper Interconnects: The Evolution of Microprocessors

Avicena Raises $25 Million in Series A to Fund Development of High Capacity microLED-based Optical Interconnects

Leadership

Bardia Pezeshki

(CEO)

After his PhD in electrical engineering at Stanford, held various managerial roles at IBM's T.J. Watson Research Center and then SDL Inc. Subsequently served as CTO at Santur Corporation, and then CEO at Kaiam Corporation.

Rob Kalman

(CTO)

Worked on photonic interconnects and optical subsystems at Optivision and ONI Systems, and has subsequently held various VP roles at Luminous Networks and Thryva (which he co-founded).

Salary benchmarks

We don't have enough data yet to provide salary benchmarks for this role.

Submit your salary to help other candidates with crowdsourced salary estimates.

Share this job

View 3 more jobs at Avicena Tech