Senior Staff/Principal Analog Design Engineer, d-Matrix

$196-300k

+ Equity + Bonus

MatLab

Expert level

San Francisco Bay Area

3-5 days a week in office (Santa Clara, CA)

AI computing and efficiency software

Be an early applicant

AI computing and efficiency software

201-500 employees

B2BArtificial IntelligenceMachine LearningSaaSAutomation

Be an early applicant

$196-300k

+ Equity + Bonus

MatLab

Expert level

San Francisco Bay Area

3-5 days a week in office (Santa Clara, CA)

201-500 employees

B2BArtificial IntelligenceMachine LearningSaaSAutomation

Company mission

To unleash the potential of generative AI to power the transformation of technology.

Job

Company

Role

Who you are

Completed a BS/MS/PhD Preferred degree in Electrical Engineering and BS 15+/MS 10+/PhD 8+ years of related professional experience in high-speed circuit design blocks such as Phase Interpolator, Clocking, PLL designs
Experience and knowledge of Schematic Capture, Spice Simulations and running Monte-Carlo simulations
Experience and knowledge of Circuit Layout, Extraction and running back-annotated simulations
Experience with Channel modeling using Matlab or other tools
Participation and contribution in Standard bodies is a plus
Must have effective interpersonal and teamwork skills
Proficiency in working with cross functional and cross site teams
Excellent communication skills
Demonstrates good analysis and problem-solving skills
Must have the ability to multi-task in a fast-paced environment

What the job involves

Analog-mixed signal integrated circuit design using (but not limited to) common circuit design tools from Cadence and Synopsys
Design state of the art In-Memory-Compute engine for Artificial Intelligence Inference Accelerator and High-Speed Die-2-Die Interface for scale-out
Job scope includes schematic circuit design, system level performance analysis, design test benches for simulations and verifications, guide layout engineers on layout in deep sub-micron process nodes from 4nm and below, and to optimize design and layout to achieve low power design performance over process-voltage-temperature corners and six-sigma Monte-Carlo yield analysis
Independent minor layout tweaks when necessary
Work with backend engineers on integration of design/layout
Provide model of circuit for backend verification
Participate in Evaluation Board design for silicon bring-up and bench debug or characterization
To build scripts for silicon bring up and test features

Our take

d-Matrix is redesigning how AI gets done, tackling the limit f traditional chips with its Corsair platform. Using digital in-memory computing and a chiplet-based design, it delivers fast, power-efficient AI interface that's built for today's data-heavy models, without the energy overload.

Recently, the company has been making some serious moves. Its secured substantial funding, with backing from Microsoft, and partnering with HTEC to boost its software capabilities. With Corsair already showing serious speed gains over GPUs like Nvidia's H100, d-Matrix is proving it can deliver real-world performance at scale.

But instead of competing head-on with GPU giants, d-Matrix is focusing on where AI meets people. And with AI growing fast, especially for interactive and generative applications, d-Matrix is building the hardware that helps AI keep up with this demand.

Freddie

Company Specialist at Welcome to the Jungle

Company

Funding (2 rounds)

Sep 2023

$110m

SERIES B

Apr 2022

$44m

SERIES A

Total funding: $154m

Company benefits

Equity
Health care
Flexible time-off
Paid paternity leave
401k retirement plan
Remote & hybrid working model
Work with world-leading engineers and researchers
Peer coaching & development
Team-building activities
Happy hours
Free food and snacks
On-site fitness center

Company HQ

Santa Clara, CA

Leadership

Sid Sheth

(Co-Founder, CEO & President)

Previously Director at NetLogic Microsystems, Director of Marketing at Broadcom Inc and SVP/GM at Inphi Corporation.

Sudeep Bhoja

(Co-Founder & CTO)

Previously CTO at Inphi Corporation, Technical Director at Broadcom and Chief Architect at Big Bear Networks.

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