Staff FPGA Design Engineer, d-Matrix

$142.5-237.5k

+ Equity + Bonus

Python

Senior and Expert level

San Francisco Bay Area

3 days a week in office (Santa Clara, CA)

AI computing and efficiency software

Open for applications

AI computing and efficiency software

201-500 employees

B2BArtificial IntelligenceMachine LearningSaaSAutomation

Open for applications

$142.5-237.5k

+ Equity + Bonus

Python

Senior and Expert level

San Francisco Bay Area

3 days a week in office (Santa Clara, CA)

201-500 employees

B2BArtificial IntelligenceMachine LearningSaaSAutomation

Company mission

To unleash the potential of generative AI to power the transformation of technology.

Job

Company

Role

Who you are

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, Master's degree preferred with a Minimum of 5+ years of experience in FPGA design and verification
Expertise in hardware design using Hardware Description Languages (HDLs) like Verilog or VHDL
Familiarity with RISC-V architecture and embedded systems development
Understanding of hardware-software integration concepts
Experience with scripting languages like Python for test automation
Strong analytical and problem-solving skills
Excellent communication, collaboration, and teamwork abilities
Thrive in dynamic environments where innovative problem-solving is key
Experience with industry-standard management protocols (MCTP, PLDM, SPDM)
Experience with platform BMC (Baseboard Management Controller)
Knowledge of power management techniques (PMBus)
Knowledge of hardware security and secure boot concepts
Experience with cloud server architectures and concepts

What the job involves

Design and verify FPGA-based solutions for d-Matrix AI inference accelerator management
Define FPGA microarchitecture specifications and collaborate with stakeholders to ensure alignment with project requirements
Develop resilient dual boot architecture for multi-core multi chiplet booting
Design and implement hardware and software modules for platform power management, health monitoring, and telemetry data acquisition
Interface with host server BMC through SMBus mailbox with management protocol overlays such as MCTP, PLDM and SPDM
Integrate RISC-V CPU cores and related firmware into FPGA designs
Develop eFuse controller within the FPGA
Design and integrate a secure boot solution adhering to NIST standards within the FPGA to enable secure booting of d-Matrix accelerator chiplets
Collaborate with cross-functional teams to ensure seamless hardware-software integration and support inference accelerator hardware bring-up and troubleshooting
Author Python scripts for hardware testing and automation

Our take

d-Matrix is redesigning how AI gets done, tackling the limit f traditional chips with its Corsair platform. Using digital in-memory computing and a chiplet-based design, it delivers fast, power-efficient AI interface that's built for today's data-heavy models, without the energy overload.

Recently, the company has been making some serious moves. Its secured substantial funding, with backing from Microsoft, and partnering with HTEC to boost its software capabilities. With Corsair already showing serious speed gains over GPUs like Nvidia's H100, d-Matrix is proving it can deliver real-world performance at scale.

But instead of competing head-on with GPU giants, d-Matrix is focusing on where AI meets people. And with AI growing fast, especially for interactive and generative applications, d-Matrix is building the hardware that helps AI keep up with this demand.

Freddie

Company Specialist at Welcome to the Jungle

Company

Funding (2 rounds)

Sep 2023

$110m

SERIES B

Apr 2022

$44m

SERIES A

Total funding: $154m

Company benefits

Equity
Health care
Flexible time-off
Paid paternity leave
401k retirement plan
Remote & hybrid working model
Work with world-leading engineers and researchers
Peer coaching & development
Team-building activities
Happy hours
Free food and snacks
On-site fitness center

Company HQ

Santa Clara, CA

Leadership

Sid Sheth

(Co-Founder, CEO & President)

Previously Director at NetLogic Microsystems, Director of Marketing at Broadcom Inc and SVP/GM at Inphi Corporation.

Sudeep Bhoja

(Co-Founder & CTO)

Previously CTO at Inphi Corporation, Technical Director at Broadcom and Chief Architect at Big Bear Networks.

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