Staff FPGA Design Engineer, d-Matrix

$142.5-237.5k

+ Equity + Bonus

Python

Senior and Expert level

San Francisco Bay Area

3 days a week in office (Santa Clara, CA)

AI computing and efficiency software

Open for applications

AI computing and efficiency software

21-100 employees

B2BArtificial IntelligenceMachine LearningSaaSAutomation

Open for applications

$142.5-237.5k

+ Equity + Bonus

Python

Senior and Expert level

San Francisco Bay Area

3 days a week in office (Santa Clara, CA)

21-100 employees

B2BArtificial IntelligenceMachine LearningSaaSAutomation

Company mission

To deliver best-in-class economics for AI inference acceleration in the datacenter.

Job

Company

Role

Who you are

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, Master's degree preferred with a Minimum of 5+ years of experience in FPGA design and verification
Expertise in hardware design using Hardware Description Languages (HDLs) like Verilog or VHDL
Familiarity with RISC-V architecture and embedded systems development
Understanding of hardware-software integration concepts
Experience with scripting languages like Python for test automation
Strong analytical and problem-solving skills
Excellent communication, collaboration, and teamwork abilities
Thrive in dynamic environments where innovative problem-solving is key
Experience with industry-standard management protocols (MCTP, PLDM, SPDM)
Experience with platform BMC (Baseboard Management Controller)
Knowledge of power management techniques (PMBus)
Knowledge of hardware security and secure boot concepts
Experience with cloud server architectures and concepts

What the job involves

Design and verify FPGA-based solutions for d-Matrix AI inference accelerator management
Define FPGA microarchitecture specifications and collaborate with stakeholders to ensure alignment with project requirements
Develop resilient dual boot architecture for multi-core multi chiplet booting
Design and implement hardware and software modules for platform power management, health monitoring, and telemetry data acquisition
Interface with host server BMC through SMBus mailbox with management protocol overlays such as MCTP, PLDM and SPDM
Integrate RISC-V CPU cores and related firmware into FPGA designs
Develop eFuse controller within the FPGA
Design and integrate a secure boot solution adhering to NIST standards within the FPGA to enable secure booting of d-Matrix accelerator chiplets
Collaborate with cross-functional teams to ensure seamless hardware-software integration and support inference accelerator hardware bring-up and troubleshooting
Author Python scripts for hardware testing and automation

Our take

The explosion in the field of AI puts significant strain on traditional computers, and the silicon architectures currently in use are a bottleneck on the speed and effectiveness of emerging AI models. d-Matrix aims to tackle this challenge by with its digital in-memory computing accelerator for AI. Using a combination of machine learning software tools and modular chiplets it delivers a huge increase in AI computing efficiency without a corresponding increase in energy use.

D-Matrix has major competitors in the race to deliver the next generation of scalable AI solutions. These include the likes of Nvidea which is developing GPU architecture that runs at ten times the efficiency of existing models. However the flexibility and easy scalability of d-Matrix's solution helps it stand out, and its novel approach has gained a high degree of support from investors. The company is currently expanding its operations in the US, India and Australia, and is well poised for success as demand for AI compute solutions continues to grow exponentially.

Freddie

Company Specialist at Welcome to the Jungle

Company

Funding (2 rounds)

Sep 2023

$110m

SERIES B

Apr 2022

$44m

SERIES A

Total funding: $154m

Company HQ

Santa Clara, CA

Leadership

Sid Sheth

(CEO)

Previously Director at NetLogic Microsystems, Director of Marketing at Broadcom Inc and SVP/GM atInphi Corporation.

Sudeep Bhoja

(CTO)

Previously CTO at Inphi Corporation, Technical Director at Broadcom and Chief Architect at Big Bear Networks.

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