Principal Design Engineer, Celestial AI

RTL Design & Integration

$200-240k

+ Bonus + equity

Python

Perl

Senior and Expert level

San Francisco Bay Area

Office located in Orange County, CA

Optical interconnect technology platform for data center and AI computing solutions

Be an early applicant

Optical interconnect technology platform for data center and AI computing solutions

101-200 employees

B2BEnterpriseManufacturingDeep TechMachine Learning

Be an early applicant

$200-240k

+ Bonus + equity

Python

Perl

Senior and Expert level

San Francisco Bay Area

Office located in Orange County, CA

101-200 employees

B2BEnterpriseManufacturingDeep TechMachine Learning

Company mission

To develop audacious AI computing platforms that elevate performance, energy and economic efficiencies, enabling our customers to rapidly deploy innovations in their AI applications.

Job

Company

Role

Who you are

MS or PhD in Electrical Engineering, Computer Engineering, or a related field preferred
8+ years of experience in SoC design, RTL development, and integration
Expertise in RTL design using SystemVerilog
Strong understanding of high-speed memory interfaces (e.g., DDR, HBM) and chip-to-chip interconnects (e.g., AXI, UCIe, PCIe, CXL)
Strong knowledge of RTL verification and validation methodologies, including Lint, CDC, STA, and LEC
Experience with low-power design techniques, including clock gating, power gating, and voltage scaling
Deep understanding of SoC architecture, including multi-core processing, coherency protocols, and subsystem integration
Proficiency with SoC design tools, including simulation, synthesis, timing analysis, and power estimation
Working knowledge of formal verification methodologies (SVA, UVM)
Experience with scripting languages (Python, Perl, TCL) for design automation

What the job involves

As a Principal Design Engineer, you will play a key role in defining and integrating architectures for Celestial AI's IP and SOCs, focusing on high-speed interfaces and chip interconnect solutions
You will collaborate closely with system architects, RTL designers, and verification teams to develop high-performance SoC designs
This role requires deep expertise in RTL design, integration, and memory subsystem architectures
Architect, design, and integrate high-performance SoC components, including high-speed memory interfaces (e.g., DDR, HBM) and chip interconnects (e.g., AXI, NoC, UCIe, CXL, PCIe)
Develop and implement complex RTL designs using SystemVerilog, ensuring scalability, power efficiency, and reusability
Lead SoC-level integration efforts, working closely with cross-functional teams on design specifications, IP integration, and performance optimization
Define synthesis constraints for modules and SOC and collaborate with Synthesis and Physical Design teams
Author detailed design specifications and documentation for SoC modules and subsystems
Collaborate with verification engineers to define test strategies, drive coverage closure, and ensure functional correctness
Optimize for power, performance, and area (PPA) by evaluating tradeoffs at both module and SoC levels
Perform static and dynamic analysis using industry-standard tools (Lint, CDC, STA, and LEC) to ensure high-quality designs
Provide technical leadership and mentorship to junior engineers and cross-functional teams

Our take

Chip production forms the backbone of our modern, digitally enabled economy; being important enough to be of major geopolitical interest, and garnering billions of investment from the US alone. Celestial AI has developed a proprietary technology platform which enables high-performance computing solutions, using light for data movement within and between chips, enabling it to deliver "the next generation of AI acceleration products".

The company's photonic-electronic technology has sparked significant interest in the AI hardware space, and has resulted in it raising impressive investment. With this funding, the company aims to expand its worldwide engineering workforce, accelerate product development, and build more strategic supplier relationships for the future.

Steph

Company Specialist at Welcome to the Jungle

Company

Funding (last 2 of 6 rounds)

Mar 2025

$250m

SERIES C

Mar 2024

$175m

SERIES C

Total funding: $588.9m

Company benefits

Equity grants
Health, dental, and vision insurance
Retirement plans
FSA
Parental leave
Flexible paid time off policy

Company HQ

Santa Clara, CA

Leadership

David Lazovsky

(Co-Founder & CEO)

Previously a Venture Partner at Khosla Ventures. Before that, Founder, President and CEO of Intermolecular developing IP-protected technology for semiconductor and clean energy customers.

Preet Virk

(Co-Founder & COO)

Previously SVP of GM Networking BU at MACOM.

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