Senior ASIC/VLSI Synthesis and Design Engineer, Celestial AI
$175-195k
Office located in Orange County, CA
Optical interconnect technology platform for data center and AI computing solutions
Open for applications
Optical interconnect technology platform for data center and AI computing solutions
101-200 employees
Open for applications
$175-195k
Office located in Orange County, CA
101-200 employees
Company mission
To develop audacious AI computing platforms that elevate performance, energy and economic efficiencies, enabling our customers to rapidly deploy innovations in their AI applications.
Role
Who you are
- Bachelor's/Master's degree in Electrical/Electronic Engineering or Computer Science. At least 10 years of experience in ASIC/VLSI design, with a focus on synthesis, design, and DFT
- Strong understanding of digital design principles, and experience with RTL coding in Verilog/SystemVerilog
- In-depth knowledge of synthesis methodologies and tools from leading EDA vendors ( Genus, Tempus, DC, PrimeTime, etc)
- Experience with writing design constraints for synthesis, timing closure, gate level simulation, and pipelining at different levels for performance optimization and timing closure
- Experience with DFT flows, including scan insertion and ATPG
- Familiarity with physical design and backend flow
- Experience with power analysis and optimization flows such as power gating, clock gating, voltage scaling, and dynamic voltage frequency scaling
- Experience with memory BIST and repair, and post-silicon validation
- Experience with deep technology nodes and very large designs
- Experience with scripting languages such as Perl, Python, or Tcl
- Excellent problem-solving skills and ability to work independently and in a team environment
- Strong communication and interpersonal skills, with the ability to interact effectively with cross-functional teams
- Proven track record of delivering successful designs on time and meeting performance, power, and area goals
What the job involves
- We are seeking a highly skilled Senior ASIC/VLSI Synthesis and Design Engineer to join our team.
- The successful candidate will be responsible for developing and implementing complex digital designs for high-performance ASICs and SoCs.
- The role will involve working closely with design teams to optimize the designs for power, performance, and area while meeting stringent time-to-market constraints.
- The ideal candidate should have a strong background in ASIC/VLSI design flow, digital design, and synthesis methodologies, as well as experience in clock level and top-level synthesis, timing closure, gate level simulation, DFT, power analysis, memory BIST and repair.
- Experience with deep technology nodes and very large designs is also essential
- Develop and implement high-performance, low-power, and area-efficient digital designs for ASICs and SoCs using industry-standard EDA tools
- Work closely with design teams to understand the requirements and constraints of the design, and provide feedback on design feasibility, timing, and power
- Write and implement block level and top level constraints for synthesis, perform timing closure, and gate level simulation
- Develop and implement synthesis flows and methodologies, and drive improvements in the design process
- Debug and resolve design issues related to synthesis, timing, power, and area
- Design and support DFT flows, including scan insertion and ATPG
- Optimize designs for power, performance, and area, and meet design goals within the given schedule. Implement memory BIST and repair, and support post-silicon validation
- Implement pipelining at different levels for performance optimization and timing closure
- Perform power analysis and optimize designs for low power
Our take
Chip production forms the backbone of our modern, digitally enabled economy; being important enough to be of major geopolitical interest, and garnering billions of investment from the US alone. Celestial AI has developed a proprietary technology platform which enables high-performance computing solutions, using light for data movement within and between chips, enabling it to deliver "the next generation of AI acceleration products".
The company's photonic-electronic technology has sparked significant interest in the AI hardware space, and has resulted in it raising impressive investment. With this funding, the company aims to expand its worldwide engineering workforce, accelerate product development, and build more strategic supplier relationships for the future.
Steph
Company Specialist at Welcome to the Jungle
Insights
Few candidates hear
back within 2 weeks
68% employee growth in 12 months
Company
Funding (last 2 of 5 rounds)
Mar 2024
$175m
SERIES C
Jun 2023
$100m
SERIES B
Total funding: $338.9m
Company benefits
- Equity grants
- Health, dental, and vision insurance
- Retirement plans
- FSA
- Parental leave
- Flexible paid time off policy
Company values
- Communicate Constructively
- Act with Integrity
- Innovate Collaboratively
Company HQ
Santa Clara, CA
Articles
Leadership
David Lazovsky
(Co-Founder & CEO)Previously a Venture Partner at Khosla Ventures. Before that, Founder, President and CEO of Intermolecular developing IP-protected technology for semiconductor and clean energy customers.
Preet Virk
(Co-Founder & COO)Previously SVP of GM Networking BU at MACOM.
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