Physical Design Engineering Manager, Astera Labs

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master's preferred
• 10+ years of experience in physical design implementation of complex SoCs at advanced nodes (7nm and below)
• 2+ years of experience leading teams or projects with demonstrated ability to mentor and develop engineers
• Hands-on expertise across the physical design flow: synthesis, place-and-route, CTS, extraction, timing closure, EM-IR, DRC/LVS, and equivalence checking
• Proficiency with Cadence Innovus and/or Synopsys Fusion Compiler/ICC2 and supporting toolchains
• Strong scripting ability in Tcl, Python, and/or Perl
• Professional attitude with the ability to prioritize a dynamic list of tasks, plan and prepare for customer meetings in advance, and work with minimal guidance
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
• Experience with Cadence and/or Synopsys physical design tools/flows

Desirable

• Astera Labs is seeking a Physical Design Engineering Manager to lead a team of physical design engineers at our Toronto site, driving the implementation of connectivity ASICs within our Signal Connectivity Group. This group is responsible for products that enable high-speed serial connectivity including PCIe retimers, Ethernet retimers, and signal conditioning solutions deployed across the world's largest AI clusters and hyperscale data centers
• As an Physical Design Manager Engineering Manager, you will combine hands-on technical leadership with people management, owning physical design execution from RTL to GDSII while building and mentoring a high-performing team. You will drive floorplanning, place-and-route, timing closure, and sign-off for complex designs requiring deep understanding of high-speed physical layer interfaces and SerDes integration at TSMC advanced nodes
• Build, lead, and mentor a physical design team, owning Physical Design execution and team development for Signal Connectivity Group products
• Drive block and top-level physical design implementation from floorplan through tapeout for retimer and signal conditioning ASICs
• Collaborate with RTL, DFT, STA, EMIR, and verification teams to drive design convergence from synthesis through sign-off
• Work with IP vendors for both RTL and hard-macro integration, ensuring placement constraints and routing guidelines are met
• Drive team execution, hiring, career development, and sprint planning for the Toronto PD team
• Establish physical design best practices, flow improvements, and quality checks to scale execution across multiple concurrent programs
• Coordinate with global PD teams (San Jose, Irvine, Bangalore) to ensure consistent methodology and design quality