Senior High-Speed PCB Layout Engineer, Array Labs
$125-160k
+ Equity
Office located in Palo Alto, CA
Space-based radars
Be an early applicant
Space-based radars
21-100 employees
Be an early applicant
$125-160k
+ Equity
Office located in Palo Alto, CA
21-100 employees
Company mission
To provide high-quality 3D imagery on a global scale.
Role
Who you are
- B.S. in Electrical Engineering, or a related field with 4+ years of relevant experience
- Experience in PCB layout, fabrication, and release of high-speed digital and mixed-signal electronics
- Excellent teamwork and communication skills
- Learns new concepts rapidly, completely, and in a self-directed manner
- High levels of self-motivation and personal accountability
- Ability to work in a fast-paced environment under significant time constraints
Desirable
- Experience designing high-speed digital and mixed-signal PCB layouts including constraint-driven routing, impedance control, and length matching
- Comfort with Altium Designer for complex layout and clean manufacturing outputs; familiarity with Allegro and/or OrCAD
- Experience developing PCB stack-ups and layout constraints for high-speed interfaces and dense, high-performance boards
- A strong intuition for layout-driven SI/PI behavior, including return paths, reference plane strategy, via transitions, and noise coupling between domains
- Experience working closely with electrical design engineers to translate schematic intent into layouts that work on the first spin
- Experience with manufacturing release, DFM/DFT considerations, and collaborating with fabrication and assembly partners
- Experience supporting lab bring-up and debug alongside design and test engineers, including investigating SI/PI issues observed on hardware
- Familiarity with SI/PI analysis workflows and tools such as Ansys SIwave, Keysight Power Analyzer, HyperLynx, or Sigrity
- Experience taking high-performance hardware from prototype through qualification and environmental testing
What the job involves
- As a Senior High-Speed PCB Layout Engineer, you will own the physical implementation of Array’s high-speed digital and mixed-signal electronics in Altium, translating schematics and performance requirements into layouts and functional designs
- Your work will include component placement, constraint-driven routing, stack-up definition, return path and reference plane strategy, and partitioning between sensitive mixed-signal domains and high-speed digital interfaces
- You will partner closely with electrical design, firmware, mechanical, and test engineers to drive layout constraints, reviews, and manufacturing releases
- The boards you ship will directly determine signal integrity, power integrity, noise performance, and overall system reliability in the lab and on orbit
- Own high-speed PCB layout from initial placement through manufacturing release in Altium
- Define and implement stack-ups, impedance targets, length-matching constraints, and reference plane/return-path strategies for high-speed interfaces
- Translate schematic intent into layouts that meet signal integrity and power integrity requirements across mixed-signal and digital domains
- Partner with electrical design, firmware, mechanical, and test engineers to develop layout constraints, run reviews, and de-risk first-pass success
- Drive DFM/DFT considerations with fabrication and assembly partners, including documentation and release artifacts
Application process
- We will conduct three interviews via Zoom; the typical process takes around 3-5 weeks to complete from start to finish
Our take
3D imaging is a growing market important to a wide array of industries, including climate action, defence, and insurance analytics. However, data supply chains from the satellites that provide this imaging to the people processing it are slow and expensive. Array Labs is developing innovative satellite imaging that can be delivered to its users almost in real-time.
Array Labs has taken part in two reputable accelerators since it was founded in 2021, and is attracting investors thanks to its plans to create a multifunctional 3D imaging satellite constellation above the Earth. Whilst this idea has been in play for decades, it is only recently that the dataset technology has caught up with the concept, and Array Labs is paving the way.
There’s still much work to be done to realise Array's ultimate vision, but it has got off to a promising start and has good funding at its back. Taking on the work ahead of it will rely heavily on partnerships with preexisting satellite companies.
Kirsty
Company Specialist at Welcome to the Jungle
Company
Funding (last 2 of 3 rounds)
Oct 2022
$5m
SEED
Jun 2022
$0.2m
SEED
Total funding: $5.8m
Company HQ
Old Palo Alto, Palo Alto, CA
Leadership
Andrew Peterson
(Co-Founder & CEO)Previously a Senior Control Systems Engineer at Moog Space and Defense Group, and a GNC Engineer and Radar Software Engineer at General Atomics Aeronautical Systems.
Isaac Robledo
(Co-Founder & COO)Previously an Associate at Sunstone Properties Trust, a CMBS Associate at Morgan Stanley, and a Financial Analyst at JLL.
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