Senior Design Verification Engineer, Astera Labs

• Experience with integrating C/C++ in System Verilog environments using DPI/PLI
• Ability to use scripting tools (Perl/Python) to automate verification infrastructure
• Experience in developing infrastructure and tests in a hybrid directed and constrained random
• Environments
• Must be able to work independently to develop test-plans, and related test-sequences in UVM to
• Generate stimuli and work collaboratively with RTL designers to debug failures
• Develop user-controlled random constraints in transaction-based verification methodology. Experience
• Writing assertions, cover properties and analyzing coverage data
• Must have prior experience using Verification IPs from 3rd party vendors for communication protocols
• Such as PCI-Express (Gen-3 and above), Ethernet, Infiniband, DDR, NVMe, USB, etc
• Develop VIP abstraction layers to simplify and scale verification deployments

Desirable

• We are looking for a Senior Design Verification Engineer with proven experience in all aspects of verification in UVM and C/C++. The candidate must have experience using high level programming languages such as C/C++ to communicate with System Verilog and/or UVM based environments to aid RTL simulation, CoSimulation and Emulation
• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is
• Required, and a Maser’s is preferred
• ≥2 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or
• Networking applications
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for
• Customer meetings in advance, and to work with minimal guidance and supervision
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in Canada and start immediately