Design Verification Engineer, Lightmatter

• Master's degree or higher in Electrical or Computer Engineering (or other related fields)
• 1-5 years of industry experience in Design Verification
• Proficiency in Hardware Description Languages (HDL) such as SystemVerilog
• Knowledge of verification methodologies such as UVM or OVM
• Proficiency in using simulation tools like Xcelium, ModelSim, Questa, or VCS
• Experience with Scripting Languages (Perl or Python)
• Fluency in English, both written and verbal
• Ability to work with diverse teams of engineers and scientists

Desirable

• As a Design Verification Engineer at Lightmatter, you will find yourself at the heart of a dynamic, interdisciplinary team
• Your role will involve close collaboration with our digital design experts, using UVM testbench techniques to rigorously verify their designs
• Your responsibilities will include working alongside photonic and analog designers, gaining a deep understanding of their innovative designs, and applying Real Number Modeling (RNM) and AMS verification methods
• This critical function ensures the integrity of their work
• We are hiring Design Verification Engineers at multiple levels
• Your interaction with the Architecture team will be crucial in comprehending system requirements and spearheading performance verification
• This role offers a unique platform to enhance your skills across a spectrum of areas including UVM, AMS modeling, mixed-signal verification, formal verification, emulation, and both performance modeling and verification
• Collaborate closely with digital, photonics, and analog designers to gain a thorough understanding of their designs and formulate comprehensive test plans for verifying their work
• Create UVM test benches for subsystem-level verification and provide support for full-chip verification. Debug test benches, identify and address issues, achieve high coverage, and ultimately sign off on Design Verification (DV)
• Develop Real Number Models (RNM) for photonics and analog Intellectual Properties (IPs) and conduct AMS verification to ensure accurate model representation. Integrate the RNM models seamlessly into the UVM test bench
• Play a key role in the development of the Golden Reference Model (GRM) for design verification and actively participate in running emulations and formal verification for DV purposes