Director of Principal Engineering Program Manager, Butterfly Network

• 12+ years leading complex, cross-functional technical programs in semiconductor, embedded hardware, deep-tech, or regulated product environments
• Demonstrated ownership of at least one full ASIC silicon lifecycle from architecture/spec freeze through tapeout, first silicon bring-up, qualification, and production ramp
• Proven ability to lead across ASIC design, packaging/test (OSAT), validation, firmware/systems integration, manufacturing/NPI, quality, and supply chain, including direct coordination with foundries and external vendors
• Experience delivering customer-facing embedded hardware products through EVT/DVT/PVT, NPI, and commercialization milestones
• Deep expertise in integrated program scheduling, phase-gate governance, tapeout readiness management, yield/ramp tracking, RAID management, critical path control, and disciplined change management
• Strong financial and resource planning capability, including budget forecasting, vendor/SOW management, and variance control
• Ability to operate at both technical and executive levels — driving cross-functional tradeoffs while delivering clear, decision-oriented updates to VP/C-level leadership
• Experience managing ambiguity, recovering from slips, and building predictable execution in complex hardware programs
• Willingness to travel as required for foundry/OSAT, customer, and manufacturing engagements
• The ideal candidate thrives in ambiguous, technically complex environments, brings strong semiconductor & system program leadership, and can manage partner programs with high efficiency and rigor

Desirable

• Butterfly is seeking a Director - Principal Program Manager to lead end-to-end program management for our silicon development and partner-facing Butterfly Embedded integrations, spanning multiple concurrent workstreams across internal roadmaps and external partner/customer programs
• Reporting to the Head of PMO, this role owns program execution from architecture through commercialization including ASIC, CMUT MEMS, packaging and V&V, and ensuring success is measured by qualified silicon in production and partner deliverables meeting technical, regulatory, and commercialization milestones
• This leader will define and operate the program management operating model (phase gates, design reviews, integrated schedules, change control), drive cross-functional execution across engineering, manufacturing, quality, regulatory, supply chain, legal, and provide clear executive level visibility and decision support
• End-to-End Execution: Own ASIC silicon chip and Butterfly Embedded hardware program lifecycles from architecture and requirements through tapeout/ prototype, bring-up, qualification, customer milestone delivery, and production ramp, ensuring predictable execution and clear readiness criteria at each phase
• Operating Model & Tooling: Define and enforce phase-gate governance, design review cadence, and a single integrated schedule across silicon, firmware, hardware, manufacturing, and customer deliverables, leveraging industry-standard PgM tools (e.g., Jira, MS Project, Smartsheet) with explicit phase exit criteria
• Cross-Functional Leadership: Drive execution across ASIC/MEMS, hardware/device software integration, validation, manufacturing/NPI, quality/regulatory, and supply chain to ensure aligned priorities and rapid issue resolution
• Partner & Vendor Management: Maintain alignment between technical priorities and external commitments; define deliverables, interfaces, and commercialization milestones; and coordinate foundries, OSATs, vendors, and customer dependencies
• Risk & Change Control: Maintain RAID logs and critical path visibility; enforce disciplined change control across scope, schedule, cost, and customer commitments; and escalate risks with clear tradeoffs and recovery options
• Budget & Resourcing: Own program resource planning, budget forecasting, and variance tracking, coordinating vendor/SOW execution with engineering, procurement, and finance
• Compliance & Logistics: Integrate applicable compliance requirements (e.g., FDA/ISO/IEC) into program plans and coordinate procurement, build planning, and logistics to support ASIC silicon chip and POCUS product hardware milestones
• Executive Reporting & Improvement: Deliver concise monthly/quarterly VP/C-level updates on status, risks, and decisions required, while continuously improving program rigor and execution scalability across ASIC silicon and POCUS product portfolios