CPU Architect, Tenstorrent
Load-Store
$100-500k
Range includes base and variable compensation targets
Building computers for AI
Be an early applicant
Building computers for AI
501-1000 employees
Be an early applicant
$100-500k
Range includes base and variable compensation targets
501-1000 employees
Company mission
To bring unique solutions to the problems facing AI and machine learning.
Role
Who you are
- We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting
- Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science (or equivalent experience)
- Strong understanding of computer architecture fundamentals, including memory hierarchy, cache coherence, and data prefetching
- Familiarity with performance modeling and simulation tools (e.g., Gem5, SimpleScalar, or similar)
- Basic knowledge of hardware description languages (e.g., Verilog, VHDL) and system-level programming (C, C++)
- Problem-solving skills and ability to analyze complex system interactions
- Excellent communication and teamwork abilities
- Hands-on experience with performance profiling tools and benchmarking methodologies
- Exposure to parallel processing architectures and multi-core systems
- Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process
What the job involves
- We are seeking a highly motivated and passionate CPU Architect to join our processor architecture team, focusing on the CPU’s load-store unit
- In this role, you will contribute to the design, analysis, and optimization of cutting-edge CPU architectures with an emphasis on a high-performance load-store unit
- This is an excellent opportunity to work alongside world class architects in high-performance computing and processor design
- Drive the architecture, micro-architecture, design and optimization of the CPU load-store unit for Tenstorrent’s high-performance out-of-order RISCV CPUs
- Propose new implementations to optimize load-store PPA
- Perform simulations, modeling, and performance analysis of advanced CPU features and state-of-the-art data prefetchers
- Collaborate with hardware and software teams to optimize memory access patterns and system performance
- Stay up to date with industry trends and emerging technologies in CPU architecture and the memory subsystem
- Support documentation and presentation of architectural decisions, trade-offs, and findings
Our take
Advances in artificial intelligence apps, combined with a global chip shortage, are strong tailwinds for chip processor Tenstorrent. The semi-conducter developer is designing specialized chips for running artificial intelligence applications, building chips for what it calls "software 2.0".
The company’s unique approach is to build for this future software, which it believes will be written at a higher level. Combining this with conditional computing, Tenstorrent supports a scalable distributed network approach that is analogous to a human brain.
While the market for specialised AI hardware is destined to be gigantic, the company has to compete with a plethora of hopeful startups (as well as major tech companies like NVIDIA and Qualcomm). That said, Tenstorrent boasts an excellent trajectory so far, with its latest moves including unveiling its high-end Wormhole AI processors, and a partnership with LG which will see the development of chips for "Affectionate Intelligence".
Kirsty
Company Specialist at Welcome to the Jungle
Insights
52% employee growth in 12 months
Company
Funding (last 2 of 7 rounds)
Dec 2024
$700m
SERIES D
Jun 2024
$300m
LATE VC
Total funding: $1.3bn
Company HQ
Flemingdon Park, Toronto, ON
Leadership
Jim Keller
(CEO)Previously Senior VP of Silicon Engineering at Intel Corporation, VP of Autopilot Hardware Engineering at Tesla, Corporate VP and Chief Architect at AMD, and VP of Engineering at Apple.
Milos Trajkovic
(Co-Founder & Director of Hardware Engineering)Former Manager of Firmware Design Engineering at AMD, and FPGA design engineer at Signum Concepts.
Ivan Hamer
(Co-Founder)Former Consulting Software/Embedded Engineer at AMD, and Senior Software Developer at iNTERFACEWARE.
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