Principal AI Infrastructure & Hardware Program Management, Astera Labs

• 12+ years of experience in hardware program management, preferably in AI, servers, storage, or networking
• Proven track record of delivering complex global hardware programs from concept to production
• Experience leading cross-functional teams across multiple geographies
• Strong background in product development lifecycle (EVT, DVT, PPVT)
• Experience working with Tier-1 customers and JDM models
• Demonstrated ability to manage program financials, timelines, and risks at scale
• Excellent communication skills with experience presenting to senior executives

Desirable

• We are seeking a highly experienced and results-driven leader to drive our global AI, Storage, and Networking hardware design programs. This role will be responsible for end-to-end program leadership across complex, multi-disciplinary initiatives, ensuring successful delivery of cutting-edge products in a fast-paced, innovation-driven environment
• You will work closely with executive leadership, Tier-1 customers, and cross-functional global teams to deliver next-generation infrastructure solutions, including advanced AI platforms
• Lead and manage global AI, Storage, and Networking hardware design programs, ensuring on-time delivery, scope control, and budget adherence
• Drive program governance, risk management, and execution excellence across all phases of product development
• Provide regular program updates, risk assessments, and financial reporting to executive leadership through structured reviews (e.g., Leadership Program Reviews)
• Oversee the successful launch of complex hardware platforms, including AI GPU-based systems
• Manage high-priority, resource-constrained programs while maintaining quality and schedule commitments
• Enable innovation in next-generation AI infrastructure and high-performance computing platforms
• Lead end-to-end program management for UALink / PCIe Gen6 switch tray development supporting rack-scale AI platforms and GPU clusters
• Coordinate design, validation, and manufacturing readiness of switch trays across EVT, DVT, and PVT phases
• Drive integration of switch silicon, retimer cards, cabling, and system-level connectivity within full rack-scale architectures
• Collaborate with ODMs and partners to align on design specifications, cost models, and development schedules
• Manage technical trade-offs across performance, signal integrity, power delivery, thermals, and scalability for high-density GPU deployments
• Partner with Tier-1 customers to deliver Joint Design Manufacturing (JDM) programs
• Ensure alignment with customer-specific requirements in design, supply chain, and quality
• Build strong customer relationships and act as a trusted advisor throughout the product lifecycle
• Lead globally distributed teams across engineering (HW/SW), supply chain, manufacturing, and quality organizations
• Coordinate teams across multiple regions (e.g., North America and Asia) to drive seamless execution
• Guide programs through EVT, DVT, and PPVT phases, ensuring technical validation across electrical, thermal, power, signal integrity, and mechanical domains