Compiler Backend Engineer, Normal Computing

• Deep experience with compiler optimization or code generation for accelerators or other non-CPU targets: scheduling, tiling, fusion, or resource allocation
• Comfort working close to hardware: you think in terms of memory bandwidth and utilization as well as asymptotic complexity
• Willingness to design compilation approaches from first principles when existing ones don't fit the hardware
• Track record of shipping optimizations that moved a measured performance number
• Comfort building software for hardware that is still evolving, from simulation through bring-up
• Fluency in Python, and familiarity with C, C++, or Rust

Desirable

• Normal's hardware runs the most memory-bound parts of large-model inference inside memory itself, rather than shuttling weights to a processor. The software that makes this programmable doesn't exist yet in any standard form. Getting a model correct on that hardware is the frontend's job; making it fast is yours
• Our hardware does not look like a CPU or GPU, so its compiler backend can't be borrowed from one. As a Compiler Engineer focused on the backend, you will help design and build the custom compilation that maps LLM inference onto it, from scheduling and memory planning to the code our hardware actually executes
• You will work at the boundary between the compiler and the hardware, closely enough to know when an optimization belongs at a different layer, or when the right answer is a new abstraction. Our chip is pre-silicon, so you will measure your work against our simulators and FPGA prototypes first, and against silicon as it arrives
• Code Generation: Build the passes that turn lowered programs into the code our hardware executes, designing new compilation approaches where conventional ones don't fit. Success means correct, efficient code for every operation our models need
• Scheduling and Memory Planning: Own how work and data are scheduled and placed across our hardware's resources, measured by utilization and end-to-end latency on LLM inference
• Fusion and Dispatch: Own fusion and dispatch decisions for LLM inference, so the hardware spends its time computing rather than moving data
• Hardware Co-Design: Work the abstraction layer between the compiler and the hardware, and feed compiler constraints back to our hardware architects while the design can still change
• Profiling and Validation: Validate every optimization with measured results from simulators, FPGA prototypes, and then silicon, and maintain a performance regression suite the team trusts
• Cross-Team Handoffs: Take lowered programs from our frontend compiler engineers, and decide with the team which operations the compiler generates and which use hand-tuned kernels